Non-volatile semiconductor memory devices, and in particular flash memory devices, are becoming increasingly popular means of storage for small devices such as digital cameras, MP3 players, cellular telephones, personal digital assistants (PDAs), laptop computers, etc. Other forms of nonvolatile memory include EPROM (Electrically Programmable Read Only Memory) and EEPROM (Electrically Erasable and Programmable Read Only Memory.
Unlike standard MOS transistors, flash memory cell transistors contain a floating gate that is electrically isolated and located between a control gate and typically a p-type substrate. Programming of a memory cell results in raising the threshold value of the transistor to a positive value as a result of electrons being injected through the insulating dielectric layer into the floating gate. Conversely, erasing results in lowering the threshold value of the transistor to a negative value as a result of electrons being removed from the floating gate. In this manner, the threshold value of the memory cell indicates its corresponding logic state. Programming is generally accomplished by using one of three major mechanisms: Fowler-Nordheim (FN) tunneling, source side [hot-electron] injection (SSI) and channel, or substrate, hot-electron injection (CHEI or SHEI).
When programming a memory cell string, there are various disturb mechanisms that tend to result in unintentional programming or erase. This problem is of particular concern when trying to program one cell on a wordline without programming the other cells on the same wordline. Since the program voltage is applied to all of the cells on a wordline during the programming of a selected cell, there exists a possibility that unselected cells may become inadvertently programmed (or erased) as well. Furthermore, the higher electric fields resulting as devices are scaled down in size and the source and drain junctions become more abrupt can lead to disturbs such as drain junction breakdown resulting in Gate Induced Drain Leakage (GIDL) whereby electrons leak into the boosted channel, and in particular, into the drain junction. Additionally, high electric fields can also lead to unintentional programming of unselected cells through FN tunneling, SSI and CHEI.
Various techniques, such as self boosting, local self boosting (LSB), and erased area self boosting (EASB), have improved the inhibition of program disturb, but still suffer from their own problems and fail to prevent program disturb in all instances. For example, in EASB, if the voltage applied to unselected wordlines is too low, channel boosting can be insufficient to prevent program disturb. Conversely, if this voltage is too high, there will be unintentional programming of memory cells on unselected wordlines as a result of tunneling. The three aforementioned techniques (and others known but not described herein) also suffer from a disturb mechanism that depends on whether or not the source-side neighbor cell is programmed. For example, if the source-side neighboring cell is programmed, it will have a negative charge on the floating gate. Since the control gate of the source side neighbor is at 0V, a highly reverse biased junction is created under the gate. This can lead to the phenomenon of GIDL resulting in a reduced boost potential, which can eventually lead to program disturb (in this case erasure). Conversely, if the source-side neighbor is erased, its threshold voltage is likely negative and the transistor of the cell may not turn off.
These programming problems, and others, become even more problematic for both selected and inhibited cells as NAND memory devices scale down to smaller geometries due to, in part, the stresses on gates and channels due to high voltages and the resultant high electric fields. Typical NAND memory fabricators attempt to manage the high voltages and electric fields using a number of approaches such as tightening distributions, selective non-scaling of certain features, or the introduction of exotic materials. Still other approaches utilize source side injection at low voltages that, unfortunately, require large memory cells, complicated fabrication processes, or both.
Therefore, what is required is a low voltage non-volatile memory programming protocol.